Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND

ABSTRACT

A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/353,570, filed Jan. 28, 2003, now U.S. Pat. No. 6,898,121; which is acontinuation-in-part of U.S. patent application Ser. No. 10/175,764,filed Jun. 19, 2002 now U.S. Pat. No. 6,894,930. This application isalso related to U.S. Pat. No. 5,867,429 entitled “High DensityNon-Volatile Flash Memory Without Adverse Effects of Electric FieldCoupling Between Adjacent Floating Gates” which is hereby incorporatedby this reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to flash electrically erasable andprogrammable read only memory (EEPROMS), and more specifically to NANDflash memory with a high memory cell density.

2. Related Art

Most existing commercial flash EEPROM products operate each memory cellwith two ranges of threshold voltages, one above and the other below abreakpoint level, thereby defining two programmed states. One bit ofdata is thus stored in each cell, a 0 when programmed into one state anda 1 when programmed into its other state. A chunk of a given number ofbits of data is programmed at one time into an equal number of cells.The state of each cell is monitored during programming so thatapplication of programming voltages stops when the threshold level of anindividual cell is verified to have moved within the range thatrepresents the value of the bit of data being stored in the cell.

In order to increase the amount of data stored in a flash EEPROM systemhaving a certain number of storage cells, the individual cells areoperated with more than two threshold level states. Preferably, two ormore bits of data are stored in each cell by operating the individualcells with four or more programmable states. Three threshold breakpointlevels are necessary to define four different threshold states. Such asystem is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which arehereby incorporated by this reference in their entirety. In multi-stateoperation, an available operating voltage range of the individual cellsis divided into an increased number of states. The use of eight or morestates, resulting in storing three or more bits of data per cell, iscontemplated. The voltage range of each state necessarily becomessmaller as the number of states is increased. This leaves less marginwithin each state to accommodate any error that might occur duringoperation of the memory system.

One type of error is termed a “disturb,” wherein electrons areunintentionally added to or taken away from a floating gate duringoperation of the memory. One source of a disturb is the presence of aleaky oxide dielectric positioned between the floating gate and anotherconductive gate of a cell. The charge level programmed onto a floatinggate of a cell changes when such a leaky oxide is present, thus leadingto the possibility that the state of the cell will be incorrectly readif the change in charge has been large enough. Since few to no errorscan be tolerated in a mass digital data storage system, a sufficientmargin for this error is provided by making the voltage range allocatedto each state sufficient to include an expanded range of voltages thatcan occur as the result of such disturbs. This necessarily limits thenumber of states that can be included in a multi-state flash EEPROMsystem since the total available voltage range is limited.

Another type of error is termed the “Yupin effect.” The Yupin effectoccurs when the neighboring cell of a selected cell is programmed afterthe selected cell itself is programmed, and the charges of theneighboring cell influence the voltage of the selected cell. Anypotential present in an adjacent cell or string may influence thereading of a selected cell, including those in the channel, floatinggate, or control gates etc. . . . Such interference from thesubsequently programmed neighbor cell distorts the voltages of theselected cell, possibly leading to an erroneous identification of itsmemory state during reading.

SUMMARY OF THE INVENTION

The present invention is an improved structure for high density NANDtype flash memory that minimizes the effect of disturbs and Yupin effecterrors.

One aspect of the invention is a NAND flash memory device formed from asubstrate. The device comprises strings of transistors. Each string hasa first select gate, a plurality of floating gates, and a second selectgate. The floating gates are formed between shallow trench isolationareas and wordlines extend across adjacent strings and extend betweenthe floating gates into the shallow trench isolation areas therebyisolating adjacent floating gates. The wordlines shield a selectedfloating gate from the potentials, and from variations in the potentialsof adjacent memory cells and components. The electric fields may emanatefrom a component located anywhere near the selected floating gate, forexample above or below or at a diagonal.

Another aspect of the invention is a flash memory device formed from asubstrate. The device comprises strings of adjacent transistors of aNAND architecture comprising a first select gate, a plurality offloating gates, and a second select gate, the plurality of floatinggates formed above the substrate, wherein the strings are separated byshallow trench isolation areas. The device has two or more discreteprogramming levels programmed by increasing a programming potentialuntil the levels are reached, wherein once the floating gates havereached a steady state a linear increase in programming potentialresults in an approximately linear increase in floating gate chargegiven a constant potential surrounding environment. Wordlines extendacross adjacent strings and between the floating gates into the shallowtrench isolation areas, such that when a floating gate of a selectedstring is read or verified, the wordline minimizes deviation from thelinear increase due to voltage variations in the surroundingenvironment.

The present invention is better understood upon consideration of thedetailed description below, in conjunction with the accompanyingdrawings of illustrative embodiments of the invention.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A is a plan view of the structure of memory array 100.

FIG. 1B is an electrical circuit diagram corresponding to the structureof FIG. 1A.

FIG. 2 is a cross section of memory array 100.

FIG. 3 is a cross section of memory array 100.

FIG. 4 is a cross section of memory array 100.

FIG. 5A is a plot of program voltage vs. time during a programoperation.

FIG. 5B is a plot of the voltage distribution of programming steps.

FIG. 5C is a plot of cell voltage vs. program voltage.

FIG. 5D is an illustration of an adjacent memory cell during a programoperation.

FIG. 5E is an illustration of an adjacent memory cell during lockout.

FIG. 6 is a flow chart of a method of forming an embodiment of thepresent invention.

FIGS. 7A–7J are cross sections of memory array 100 at various stagesduring the fabrication process.

DETAILED DESCRIPTION OF THE INVENTION

The following is a detailed description of illustrative embodiments ofthe present invention. As these embodiments of the present invention aredescribed with reference to the aforementioned drawings, variousmodifications or adaptations of the methods and or specific structuresdescribed may become apparent to those skilled in the art. All suchmodifications, adaptations, or variations that rely upon the teachingsof the present invention, and through which these teachings haveadvanced the art, are considered to be within the scope of the presentinvention. Hence, these descriptions and drawings are not to beconsidered in a limiting sense, as it is understood that the presentinvention is in no way limited to the embodiments illustrated.

FIG. 1A illustrates a plan view of an embodiment of the NAND flashmemory of the present invention. FIGS. 2–4 are cross sections takenthrough the structure shown in FIG. 1A. An electrical equivalent circuitof the memory array is given in FIG. 1B, wherein common elements withinthe structure of FIGS. 1A and 2–4 are identified by the same referencecharacter.

Parallel wordlines 106 connect adjacent NAND strings of floating gates102. The wordlines 106 are illustrated horizontally, and the strings areillustrated vertically in the figures. A NAND string generally includesa select gate followed by several floating gates and another selectgate. The bitline A, B, and C (BL_(A), BL_(B), BL_(C)) locationscorrespond to the string locations in the plan view, although thebitlines are generally located in another plane. The circuit diagram ofFIG. 1B most clearly shows the vertical array of strings. In this casesixteen floating gates and thus sixteen wordlines are illustrated perstring, however, the number of floating gates may be thirty-two or more,and is foreseen to increase in the future. Floating gates 102 areisolated from adjacent floating gates by isolation trenches 104.Isolating trenches 104 are also referred to as shallow trench isolationareas. The select gate line 105 on the source side (“SS”) is continuousbetween trenches 104, as can be seen in section C-C of FIG. 4. It is notetched into individual floating gates. At the end of the wordline 106above SS 105, each NAND string is electrically connected to SS 105 witha via, most easily seen in FIG. 1B an FIG. 3.

Metal bitlines 116 (only one of which is shown for the sake of clarity)connect to the N+ regions 114 within substrate 108 to sense amplifiersfor reading the charge stored in the floating gates 102. Thus, to read aparticular floating gate a string is selected via the bitline and awordline is also selected. The metal bitlines are generally, but notnecessarily, formed in a conductive layer insulated from the wordlines.At the end of each string is another select gate coupled to the drain(“SD”). The drain and source can be interchanged in some configurationsand more than 16 transistors can also be present in each string, thusalso increasing the number of wordlines.

As seen in FIG. 2, there is a portion of gate oxide 112 between eachfloating gate 102 and the substrate 108. A dielectric material 110separates the wordlines 106 from the floating gates 102 and theisolation trenches 104. Adjacent floating gates 102 are isolated fromother floating gates in the same wordline, not only by isolatingtrenches 104, but also by wordlines 106. Wordlines 106 extend downbetween floating gates into isolation trenches 104, until, within, orpast the level of gate oxide layer 112. This has several distinctbenefits.

It reduces Yupin effects between adjacent cells in the wordlinedirection. Also, it improves the cell coupling ratio between thewordlines and the floating gates. The portion of the wordline thatextends into the isolation trenches, to or past the depth of thefloating gates, increases the overlap of the surface areas and volumesof the wordlines and floating gates. This increased overlap results inbetter coupling when a charge is read or stored during program, read, orerase operations.

The electrical field across the dielectric layer 110 between adjacentfloating gates is reduced, therefore reducing any leakage currentthrough the dielectric layer that may occur as a result of theelectrical field. The lesser the electrical field, the lesser theleakage current between two adjacent floating gates. Additionally, theleakage current path is greatly increased by the extended wordlines 106.Any leakage current must travel down and around the extended portion ofthe wordlines and then back up or over to the adjacent floating gates.The charge level programmed onto a floating gate of a cell changes whensuch a leakage current is present. Therefore, by minimizing the leakagecurrent, and thus any change in charge of the floating gates, anincreased number of levels can be discerned more reliably. This leads toa higher capacity, more cost efficient, and more reliable data storagesystem.

Additionally, the extended wordline shields a selected floating gatefrom field effects of nearby channels. In certain program, read, andverify operations, a floating gate that has been programmed with aparticular charge may, in a subsequent read or verify operation,indicate that it has a larger charge than it should due to a potentialor charge in an adjacent channel. This is especially true withcomplicated program, read, and verify operations in multi-state NANDflash memory where multiple operations are occurring simultaneously inadjacent strings and cells. In many prior systems, every other cellalong one row is part of the same page; in newer systems, every cellalong one row can be part of the same page. Referring again to FIG. 2,this would mean that in a prior system, the floating gate 102A activatedby BL_(A) and the floating gate 102C activated by BL_(C) would beprogrammed while the floating gate 102B activated by BL_(B) is notprogrammed. In newer systems, every cell along one row can be part ofthe same page. Thus, as seen in FIG. 2, floating gate 102A of the stringactivated by BL_(A) may be undergoing a programming operation at thesame time as floating gate 102B. This will be discussed in furtherdetail later in reference to FIGS. 5D and 5E. In this way, twice thenumber of cells may be programmed and or verified at the same time.Although this may be efficient, it results in additional field effectproblems during all of the various operations involved in data storageoperations.

The relationship between the distribution and the incremental voltage ofthe programming pulses holds true only if the potential of any othercoupling element to the floating gates of the cells being programmedremains constant. In the case of programming adjacent NAND strings, anadjacent (substrate) channel of an adjacent cell may be at a lowpotential, for instance 0V, for a number of programming pulses while itis being programmed and then suddenly be boosted or “locked out” forsubsequent programming pulses to a high potential, for instance, 5, 7.5,or 10 V, after it verifies in order to stop further programming or forany other reason. This boosting of the channel potential also increasesthe floating gate potential of the adjacent cell. Thus, both theadjacent channel and adjacent floating gate will couple a higherpotential to the selected cell for the next programming pulse which maybroaden the width of the programmed distribution. This has a number ofnegative consequences, some of which may include error in reading aparticular bit and reduction in the total number of bits of data thatmay be stored in a given die size. An example of some programmingdetails is illustrated in FIGS. 5A-5E which will be discussed below. Thelevels given are illustrative and only serve to educate the reader onthe operation of an example memory system with which the presentinvention may be particularly advantageous.

For further information regarding the data storage operations, pleaserefer to. U.S. patent application Ser. No. 09/893,277, filed Jun. 27,2001, entitled “Operating Techniques For Reducing Effects Of CouplingBetween Storage Elements Of A Non-Volatile Memory Operated In MultipleData States,” hereby incorporated by this reference in its entirety, andan article entitled “Fast and Accurate Programming Method forMulti-level NAND EEPROMs”, pp. 129-130, Digest of 1995 Symposium of VLSITechnology, which is also hereby incorporated by this reference in itsentirety, and discusses the timing and voltage levels of programmingpulses using in the read/verify and programming operations.

An example of the incremental voltage steps of the programming pulsesare shown in FIG. 5A. In the example shown and described, the pulses areincremented by 0.2 volts. After each pulse, there is a verify cycle,followed by an incrementally higher voltage pulse. This takes placeuntil a desired or threshold voltage is verified in the floating gate.For example, this may take place until the floating gate is verified at2.0 volts.

FIG. 5B illustrates that for each program pulse, there is a distributionof the charge stored in the floating gates. For example, with the firstpulse of 16.0 volts, the distribution of the verified charges is aboutthree volts. So, if it is desired to store 2.0 volts on the floatinggate, it may be necessary to increment up to 17.0 volts and higher inthe control gate or wordline. If, for example, after a 17.0 voltprogramming pulse the distribution of stored charges on the floatinggates is such that there are some floating gates above and some belowthe 2.0 V threshold, those below will receive a further programmingwhile those above the threshold will not by having their channel boostedor “locked out.”

With a constant environment, i.e. one where the potential and electricfield of the neighboring components is constant, the programming pulses,will, after having reached a steady state, result in a predictable andapproximately linear increase in the cell voltage (V_(t)), as seen inFIG. 5C. As seen in the nearly parallel lines, some “fast” floatinggates may reach the desired verify V_(t) at a lower program voltage thanother “slow” or “intermediate” floating gates. Once the steady state hasbeen reached, it can be seen that a linear increase in the programvoltage results in a nearly linear increase in V_(t).

Therefore, if, for example, a cell has a V_(t) of 1.99 volts it willreceive another programming pulse to take it above the 2.0 voltthreshold. In a constant environment, the cell should then have a V_(t)of 2.19 volts. However, if there is any deviation of the voltage orelectric field that is applied to the cell, for example between oneprogramming pulse and another, the voltage stored on the cell may differfrom that expected. If a neighboring component exerts an influence ofthe electrical field of the cell during a programming pulse, the chargestored will also deviate. For example, the cell that was at 1.99 voltsin the previous verification cycle, may instead of having a V_(t) of2.19 volts may have a V_(t) of 2.29 or 2.39 volts. As shown in FIG. 5C,coupling of potential from a nearby cell may cause one of theintermediate cells to deviate from the linear increase that ischaracteristic of the steady state. Thus, the distribution of the cellsshown in FIG. 5B will increase due to any variation in the potential ofadjacent components.

The increase in the distribution of cells will lessen the number ofstates that can be repeatably and reliably discerned in a multi-levelstorage system. This greatly lessens the storage capacity of a memorydevice with a given die size, and therefore increases the cost ofproduction of a storage device with a desired storage capacity.

Specifically, as can be seen in FIGS. 5D and 5E, the voltages in thecomponents of an adjacent cell will vary greatly during program andduring “lockout.” An adjacent cell is any cell located near anothercell, in any direction, including diagonally. For example, floating gate102A is adjacent to floating gate 102B. The active area of the cellcomprises the channel area in the substrate below the floating gate andthe wordline area above the floating gate. The cell may also be said tocomprise portions of the shallow trench isolation area and othercomponents. A cell is “locked out” by isolating its correspondingbitline if it has verified at the desired program voltage. In theexample given above, if the cell has verified at 2.0 volts, it will be“locked out” from further programming pulses by increasing the cellvoltage in the channel (substrate) to a relatively high voltage level byisolating the corresponding bitline.

FIG. 5D shows an adjacent cell during the programming operationspreviously discussed. The shape and configuration of the cells issimplified for ease of understanding. In the example programmingoperation shown, wordline 106 of the cell is at 18 volts, floating gate102 is at 10 volts, and substrate 108 is at 0 volts. However, duringlockout, as shown in FIG. 5E, wordline 106 is now at 18.2 volts,floating gate 102 is now at 13 volts, and substrate 108 is now at 8.0volts. The channel is a portion of the substrate just below the uppersurface of the substrate. While a selected cell is being programmed, anadjacent cell may be either in the program operation shown in FIG. 5D,or the lockout state shown in FIG. 5E. Furthermore, the voltages shownin the program operations vary with the different programming pulsesdiscussed earlier. All of these voltages shown in an adjacent cell maycouple to a selected cell during programming. It is the variation inthese voltages that may result in the variation from steady stateprogramming (FIG. 5C) and thus increased deviation (FIG. 5B).

FIG. 6 is a flowchart of the steps of making memory array 100 whichshould be referred to in tandem with FIGS. 7A-7J. The memory array 100is fabricated in a substrate 108. Substrate 108 preferably comprisessilicon but may also comprise any material known to those in the artsuclvas Gallium Arsenide etc. . . First, a gate oxide layer 112 isformed upon substrate 108 in step 505 as seen in FIG. 7A. Gate oxide 112is preferably grown on substrate 108 but may also be deposited. Gateoxide layer 112 preferably comprises silicon dioxide but may differdepending on what type of substrate is used and other processing factorsor elements introduced during processing. For example, for CMOSapplications, gate oxide 112 may comprise materials (known as ETO)including nitride/oxynitride. Next, a first gate layer 102a is depositedupon gate oxide layer 112 in step 510 as seen in FIG. 7B. The first gatelayer 102a is made of semiconducting material such as polysilicon. Anitride layer 120 is then deposited upon the first floating gate layer102a in step 515 as seen in FIG 7C. In step 520, parallel trenches areetched in substrate 108 with well known etching techniques. Generally infabricating high density memory arrays where the features are of a verysmall scale, plasma etching is preferred over wet etching in order tohave a precise and uniform etch. In step 525 the trenches are thenfilled with a field oxide, as seen in FIG. 7D, to form isolationtrenches 104. The field oxide within isolation trenches 104 ispreferably comprised of silicon dioxide but can be comprised of otherinsulating materials (including materials other than oxides). Isolationtrenches 104 range from about 0.2 microns to about 0.25 microns wide andare preferably about 0.2 microns wide. The remaining field oxide 124 isremoved via chemical-mechanical polishing (“CMP”) in step 530, as seenin FIG. 7E.

Next, in step 535, nitride layer 120 is etched away such that isolationtrenches 104 extend above the surface of the first gate layer 102a, asseen in FIG. 7F. The isolating trenches 104 may extend above thesubstrate 108 and gate oxide layer 112 as shown, or, alternatively, mayonly extend up to the level of either the substrate 108, gate oxidelayer 112, or first gate layer 102a, and it should be understood thatdiffering processes and steps may be necessary to achieve thesediffering embodiments.

A second gate layer 102b of the same semiconducting material as thefirst gate layer 102a is then deposited upon the gate oxide layer 112and isolation trenches 104 in step 540. It is then selectively etchedabove isolation trenches 104 to create floating gates 102 in step 545.The resultant structure can be seen in FIG. 7G. Floating gates 102 aresubstantially “T” shaped in order to maximize the coupling between thefloating gate and the control gate, also referred to as the wordline 106that activates the floating gate. The line between the first and secondgate layers 102a and 102b has been removed for the sake of clarity. TheT shape provides a large surface area between floating gate and thewordline, thus maximizing the coupling ratio between the two devices forimproved read, program and erase operations. For further information,please refer to co-pending U.S. patent application Ser. No. 09/925,102to Yuan et al., entitled “Scalable Self-Aligned Dual Floating GateMemory Cell Array and Methods of Forming the Array,” which is herebyincorporated by this reference in its entirety.

As seen in FIG. 7H, a set of parallel trenches 122 is formed withinisolating trenches 104 in step 550. Trenches 122 may extend withintrenches 104 to the level of the upper surface of gate oxide 112 or anydistance within trenches 104 within or below the level of gate oxide112. Isolation layer 110 is then deposited upon the floating gates 102,and within second trenches 122 in isolation trenches 104, in step 555,as seen in FIG. 7I. Isolation layer 110 is preferably a dielectric layersuch as an oxide-nitride-oxide (“ONO”) layer 110. The dielectric layer110 can be any type of dielectric known in the art and is notnecessarily limited to an ONO structure. A wordline layer comprising asemiconducting material layer such as polysilicon and a conductive layersuch as tungsten suicide is then deposited upon dielectric layer 110 instep 560, as can be seen in FIG. 7J. Wordlines 106 are then etched fromthe wordline layer in step 565.

As previously mentioned, the wordlines 106 extend down between thefloating gates 102 into the isolating trenches 104. This isolatesadjacent floating gates 102 from each other. In the preferredembodiment, wordlines 106 extend within the isolation trenches 104 to orbeyond the level of the gate dielectric 112.

The various layers can be formed and the etching steps can be performedin many different well known methods and orders, and are not necessarilydone in the order described, i.e. gate oxide layer 112 may be formedbefore or after the parallel trenches are etched into substrate 108 etc.. . . Furthermore, additional layers, steps, and resultant structuresthat are not described may also be part of the process and the resultantmemory array.

The extended wordline reduces the problem of the aforementioned Yupineffect because it acts as a shield between adjacent floating gates.Again, in short, the Yupin effect is when the charge stored or otherwisepresent in a neighboring cell influences the reading of a selected cell.The present solution shields gates to avoid or minimize Yupin effecterrors caused by neighboring gates. Yupin effect errors can also beaccommodated through program and read circuitry and algorithms.

The extended wordline also protects against conduction leakage betweenadjacent floating gates within the dielectric layer 110 because itblocks the conduction path between adjacent gates. Furthermore, anypossible stringers as a result of an incomplete etch of the floatinggate layer that might short circuit adjacent gates are also-eliminatedin the situation where the etch within the isolation trench extends pastthe upper (top of the “T”) portion of the T shaped floating gate. Formore information on the Yupin effect and on disturbs, please refer toU.S. Pat. No. 5,867,429, which was previously incorporated by reference.

While embodiments of the present invention have been shown anddescribed, changes and modifications to these illustrative embodimentscan be made without departing from the present invention in its broaderaspects. Thus, it should be evident that there are other embodiments ofthis invention which, while not expressly described above, are withinthe scope of the present invention and therefore that the scope of theinvention is not limited merely to the illustrative embodimentspresented. Therefore, it will understood that the appended claims setout the metes and bounds of the invention. However, as words are animperfect way of describing the scope of the invention, it should alsobe understood that equivalent structures and methods while not withinthe express words of the claims are also within the true scope of theinvention.

1. A multi-state flash memory device formed from a substrate in whichindividual memory cells can store multiple bits represented as chargesof more than two possible levels, the device comprising: a plurality ofstrings of transistors of a NAND architecture, each string of theplurality of strings comprising a first select gate, a plurality offloating gates, and a second select gate, the plurality of floatinggates formed above channel regions in the substrate and separated fromthe channel regions, wherein a controller circuit is adapted to causeadjacent first and second strings of the plurality of strings to undergoprogramming operations at the same time, the programming operationsincluding setting different voltages levels in floating gates of theadjacent first and second strings, and wherein when the plurality ofstrings of transistors is arranged such that, during programming of aselected floating gate of the first string, a change in a potential of aportion of the second adjacent string is shielded from the selectedfloating gate of the first string by a wordline extending acrossadjacent strings and extending between floating gates of the first andsecond strings into a shallow trench isolation trench between thechannel regions of the first and second strings.
 2. The flash memorydevice of claim 1 wherein the wordline shields the selected floatinggate of the first string from a potential in the substrate at the secondstring.
 3. The flash memory device of claim 1 wherein the wordlineshields the selected floating gate of the first string from a potentialof the adjacent floating gate of the second string.
 4. The flash memorydevice of claim 1 further comprising a gate oxide layer between thefloating gates and the substrate, the wordline extending down past thelevel of an upper surface of the gate oxide layer.
 5. The flash memorydevice of claim 1 wherein the wordline shields the selected floatinggate of the first string from the potential of a floating gate of thesecond adjacent string.
 6. A flash memory device comprising: a pluralityof strings of adjacent transistors of a NAND architecture, individualstrings of the plurality of strings comprising a first select gate, aplurality of floating gates, and a second select gate, the plurality offloating gates formed above a substrate; shallow trench isolationtrenches between adjacent ones of the plurality of strings; wordlinesextending across the plurality of strings and extending between floatinggates into the shallow trench isolation trenches between adjacentstrings of the plurality of strings, wherein in the case of programmingadjacent strings of the plurality of NAND strings, a channel of a firststring adjacent a floating gate of a second string is at a firstpotential for a number of programming pulses and is at a secondpotential during subsequent programming pulses, wherein the potential ofthe channel of the first string couples to the potential of the floatinggate of the second string, and wherein the wordline shields the floatinggate of the second string from the potential of the channel of the firststring thereby affecting the coupling to the potential of the floatinggate.
 7. The flash memory device of claim 6 further comprising a gateoxide layer between the floating gates and the substrate, the wordlinesextending down past the level of an upper surface of the gate oxidelayer.
 8. The flash memory device of claim 6 wherein the wordlinesextend down past the level of an upper surface of the substrate.
 9. Theflash memory device of claim 6 wherein the wordlines extend down pastthe lower level of the channel.
 10. A flash memory device formed from asubstrate, the device comprising: a plurality of strings of transistorsof a NAND architecture, each string of the plurality of stringscomprising a first select gate, a plurality of floating gates, and asecond select gate, the plurality of floating gates formed above thesubstrate, a plurality of control gates, each control gate of theplurality of control gate overlying a floating gate; the plurality offloating gates formed above a gate oxide layer formed upon cell channelregions within the substrate; and a plurality of wordlines that extendacross the plurality of strings to connect control gates of differentstrings and that extend between the floating gates of adjacent strings,each wordline of the plurality of wordlines extending down past an uppersurface of the substrate to shield a selected floating gate during aread or verify operation from a potential present in an adjacent string.11. The flash memory device of claim 10 wherein a wordline of theplurality of wordlines shields the selected floating gate from thepotential of the substrate beneath the adjacent string.
 12. The flashmemory device of claim 11 wherein a wordline of the plurality ofwordlines shields the selected floating gate from the potential of achannel region of the substrate beneath the adjacent string.
 13. Theflash memory device of claim 10 wherein a wordline of the plurality ofwordlines shields the selected floating gate from a potential of afloating gate of the adjacent string.
 14. A multi-state flash memorydevice formed from a substrate in which individual memory cells canstore multiple bits represented as charges of more than two possiblelevels, the device comprising: a plurality of strings of transistors ofa NAND architecture arranged longitudinally in the memory device, eachstring of the plurality of strings comprising a first select gate, aplurality of floating gates, and a second select gate, the plurality offloating gates formed above channel regions in the substrate andseparated from the channel regions; wherein a controller circuit isadapted to cause adjacent first and second strings of the plurality ofstrings to undergo programming operations at the same time, theprogramming operations including setting different voltages levels infloating gates of the adjacent first and second strings, and structurein the NAND architecture that at least partially shields a change in apotential of a portion of one adjacent string from a selected floatinggate of another adjacent string when the other adjacent string isprogrammed by a wordline situated transversely over adjacent strings andincluding shielding portions extending towards the substrate betweenfloating gates of the first and second strings.
 15. The flash memorydevice of claim 14 wherein the wordline shields the selected floatinggate of the other adjacent string from the potential of a floating gateof the one adjacent string.
 16. A multi-state flash memory device formedfrom a substrate in which individual memory cells can store multiplebits represented as charges of more than two possible levels, the devicecomprising: a plurality of strings of transistors of a NAND architecturearranged longitudinally in the memory device, each string of theplurality of strings comprising a first select gate, a plurality offloating gates, and a second select gate, the plurality of floatinggates formed above the substrate, a plurality of control gates, eachcontrol gate of the plurality of control gate overlying a floating gate,the plurality of floating gates formed above a gate oxide layer formedupon cell channel regions within the substrate; wherein a controllercircuit is adapted to cause adjacent first and second strings of theplurality of strings to undergo programming operations at the same time,the programming operations including setting different voltages levelsin floating gates of the adjacent first and second strings, and aplurality of wordlines situated transversely over the plurality ofstrings to connect control gates of different strings and that includeshielding portions extending towards the substrate between the floatinggates of adjacent strings, to shield a selected floating gate during aread or verify operation from a potential present in an adjacent string.17. The flash memory device of claim 16 wherein a wordline of theplurality of wordlines shields the selected floating gate from apotential of a floating gate of the adjacent string.
 18. Inmanufacturing a memory device to have a plurality of memory cells havingfloating gates in which a programmable charge from among more than twolevels is to be stored such that individual memory cells can representmultiple bits, the plurality of memory cells arranged over a substrateto form columns along a longitudinal direction and rows along atransverse direction, the memory electrically arranged such that bitlines corresponding to the columns are situated along the longitudinaldirection, and word lines corresponding to the rows are arranged overthe memory cells along the transverse direction, a method of shieldingmemory cells from one another, the method comprising: arranging theplurality of word lines in rows along the transverse direction overcorresponding rows of the memory cells such that each of the word linesis capacitively coupled with memory cells of a corresponding row;providing a controller circuit that is adapted to cause adjacent firstand second strings of the plurality of strings to undergo programmingoperations at the same time, the programming operations includingsetting different voltages levels in floating gates of the adjacentfirst and second strings, and forming the plurality of word lines suchthat each word line includes a set of shielding portions extendingtowards the substrate between adjacent memory cells of the row of memorycells corresponding to that word line, thereby causing the word lines toat least partially shield the adjacent memory cells from one another.19. A flash memory device comprising: strings of adjacent transistors ofa NAND architecture comprising a first select gate, a plurality offloating gates, and a second select gate, the plurality of floatinggates formed above a substrate, with a channel of a first stringadjacent a floating gate of a second string at a first potential for anumber of programming pulses and at a second, different potential for asubsequent number of programming pulses; and means for controlling thefloating gates to be programmed at the same time to different levels andfor shielding the floating gates from variations of adjacent potentialfields during and between program pulses, the means for controlling thefloating gates and for shielding the floating gates being situated overthe floating gates and extending toward the substrate between thefloating gates.
 20. In a memory having a plurality of strings of memorycells arranged to form columns across a substrate surface andindividually including a floating gate, wherein the strings of memorycells are separated by dielectric between them, and wherein a pluralityof word lines extend across rows of memory cell floating gates thedielectric therebetween, a method of programming charge levels on anindividual row of memory cells to defined states, comprising:alternatively applying program pulses to and reading the states ofmemory cells along the row, in response to reading that a memory cellalong the row has reached its defined state, ceasing to apply anyfurther programming pulses to such a memory cell while continuing toapply programming pulses to other memory cells in the row until all ofthe memory cells along the row have reached their defined states, andutilizing shielding between the floating gates in the row during thealternate application of program pulses to and reading the state of thememory cells along the row by maintaining portions of the word linesbetween adjacent floating gates and extending toward the dielectrictherebetween.
 21. The method of claim 20, wherein in using theshielding, the dielectric fills trenches formed into the substratesurface between the strings of memory cells.
 22. The method of claim 21,wherein providing shielding includes maintaining the word lines belowthe level of the substrate surface.
 23. The method of claim 22, whereinapplying program pulses includes applying programming pulses that aresuccessively increased in magnitude.